This invention relates in general to electronic surface mount components, and more particularly to the thermal dissipation packaging of such components.
Electrical surface mount components facilitate the manufacturing of electronic products. Existing surface mount power transistor packages attempt to combine small size, low cost, and high thermal dissipation. These packages, however, face challenges in providing adequate heat sinking for the active device. Decreases in gain, increases in current drain, and reduced transistor life are all issues when designing high power transistor packages.
FIG. 1 is a bottom view of a prior art field effect transistor (FET) package 100 having drain 102, gate 104 and source 106 contacts formed about a plastic molded package 110. The small size of package 100 is beneficial to cost and electrical performance, but thermal dissipation is severely hampered by the necessity to remove heat from the device. To heat-sink package 100, the source contact 106 is coupled to a bottom metalized surface 108 which provides a ground surface area through which to dissipate heat. When mounted to a printed circuit board (PCB) 802, shown in FIG. 8, metalized surface 108 aligns with solder filled vias 804 and heat spreader 806 to draw heat away from the package 100. Thus, the heat sinking capability of package 100 is limited to the bottom of the device.
There have been attempts to avoid the disadvantages of heat sinking through a PC board, some more successful than others. One attempt turns a traditional leaded surface mount part upside down and folds the electrical connection leads underneath the part to make contact with exposed metal from above. The main disadvantage to this approach, and that of others, is that the leads are so long that significant parasitic inductance affects the electrical performance of the circuit.
Accordingly, a package that would enhance thermal dissipation capability would be highly desirable.